1. Field of the Invention
The current invention generally relates to dynamic logic. More particularly, the present invention is directed to masking of certain inputs in dynamic logic.
2. Description of the Related Art
Modern electronic systems, such as digital computers frequently have a need for very fast compares of many bits. A dynamic OR is advantageously used for such compares (i.e., OR logic having a precharge phase and an evaluate phase). The dynamic OR, with suitable plus or minus phase of a number of bits to be compared, is a simple and fast structure. A dynamic OR typically has an inverting buffer, making the compare function a “NOR”. It will be understood that discussion of a dynamic OR also includes a dynamic OR with an inverting buffer, providing a “NOR” function.
Often a field of data in an electronic system, such as an address, must be tested to see if that address is of interest, and such testing (comparing) must be done very quickly in order to provide fast throughput through the electronic system. For example, if a simple four-bit address is to be tested for having a value of ‘1000’, an OR is used, with the leftmost bit being inverted. When the address value is ‘1000’, the OR circuit drives a “0” (or, with an inverting buffer, making it a NOR circuit, a “1” is driven). The OR circuit drives a “1” (or, with an inverting buffer, a “0”) is driven for all other values of the address.
Many such electronic systems require masking portions of the data presented to the dynamic OR, and incur inefficiencies and signal path delays associated with data bits that require masking. For example, at a particular time, a particular 64-bit double word might only have valid data in a first 32-bit portion of the 64-bit double word. Some bits of a second 32-bit portion of the 64-bit double word might have “1” values, although the second portion is not intended to influence the output of the dynamic OR. FIGS. 1A, 1B illustrate this situation. In FIG. 1A, bits X0–X31 are valid data to be used in the compare; bits X32–X63, at a particular time, are not to be used in the compare. At other time, all 64 bits are needed in the compare. FIG. 1B shows a conventional dynamic OR 100 that mask bits X32–X63 under control of input signal “MASK”. ANDs 102A and 102B output “0” when MASK is “0”, but, respectively pass data on bits X32 and X63 when MASK is “1”. ANDs 102A and 102B add a stage of logic, with attendant delay, to the delay path of signals arriving from bits X32 and X63 (and similar bits in the masked portion of data input to dynamic OR 100). Dynamic OR 100 includes a clock buffer 101 that passes a system clock (system clk) as signal CLKX when an enabling signal (ACTIVATE) is active. PFET (P-channel field effect transistor) P5 precharges node 108 during a precharge phase when CLKX is low. During an evaluate phase, when CLKX is high, P5 does not conduct, and CLKX turns on NFETs (N-channel field effect transistors) N1–N4. If any of the inputs to NFETs N5-N8 (i.e., outputs of ANDs 102B, 102A, and bits X31 and X0, respectively are “1”, node 108 is discharged to ground. The dots between the stacks of NFETs simply indicate that not all 32 stacks in portion 105 (i.e., masked bits X32–X63) or all 32 stacks in portion 106 (i.e., bits X0–X31) are shown. Further, ANDs 102A, 102B are just two of 32 ANDs needed to mask the 32 bits (X32–X63), with the remaining ANDs not shown, but indicated by dots between ANDs 102A and 102B. Portion 105 receives as inputs the portion of the group of bits input to the dynamic OR requiring masking; portion 106 receives as inputs the portion of the group of bits input to the dynamic OR that does not require masking.
Keeper 110 is an optional block, including inverter 111 and PFET P6, which weakly maintains node 108 at an uplevel if CLKX remains “1” for an extended period of time relative to a rate of leakage that would over time discharge node 108. PFET P6 must simply be strong enough to overcome leakage that, in time, would discharge node 108. Inverter 115 drives an output 120 of dynamic OR 100. Keeper 110 is needed if node 108 must retain a “1” (undischarged state) during an extended evaluate phase of CLKX.
Typically in such applications, a critical data path from a timing standpoint is data propagation (e.g., X0–X63 to output 120). Insertion of ANDs 102A and 102B adds delay to the critical data path of data bits X32–X63. The delay path of data bits X0–X31 do not have the added delay of blocks such as ANDs 102A and 102B.
A dynamic OR is shown as the dynamic circuit in FIG. 1B. A dynamic OR was used for exemplary purposes because of its simplicity and because of its common use. It will be understood however, that other dynamic circuits also require certain inputs to be maskable.
Therefore, there is a need for a method and apparatus that provide for masking of one or more portions of a dynamic circuit without incurring additional delay.